1. Field of the Invention
This invention is related to synchronization of digital data formed by sampling analog signals and transmitted on a digital interface from the sampling device to a receiving and converting device. More particularly this invention relates to methods and devices that eliminate data xe2x80x9coverrunxe2x80x9d or xe2x80x9cunderrunxe2x80x9d due to differences in the sampling times of the sampling device and receiving and converting device.
2. Description of the Related Art
To understand the problem solved by this invention, refer now to FIG. 1. An analog electrical signal 100 is created by a transducer such as a microphone in response to a physical phenomenon. The analog electrical signal is the input to an analog-to-digital converter (ADC) circuit 105. At periodic conversion times established by the timing signal CLKIN 115, the ADC circuit 105 have an output digital signal 110 indicating the magnitude of the analog electrical signal at each of the periodic conversion times. The output digital signal 110 is then transferred to a transmitter 120 for transmission on a communication link 125. The communication link may be a telephone connection or any other known digital communication protocol.
Often digital communication protocols divide the output digital signal 110 into frames or blocks for transmission on the communication link 125. Plots 200 and 205 respectively of FIGS. 2a and 2b show a single frame of data consisting in this instance of 32 digitized samples of the analog signal. Depending on the digital communication protocol each frame of the digitized samples has a header and trailer (not shown) appended respectively to the frame of the digitized samples. The header and trailer contain information such as timing, error detection cods, source and destination codes, and beginning and ending of transmission codes.
The header and trailer information is appended in the transmitter 120 and removed in the receiver circuit 130 after receiving the frame of the digitized samples.
The received digitized samples 140 are then transferred to a digital-to-analog converter (DAC) circuit 145. The DAC circuit converts the received digitized samples 140 to an analog output signal 150. The analog output signal 150 is used to drive an output transducer such as a speaker to convert the analog output signal 150 to a physical phenomenon.
The receiver circuit 130 and DAC circuit 145 are each synchronized by the timing signal CLKOUT 135. For a communication network as shown in FIG. 1 to operate error free, the timing signals CLKIN 115 and CLKOUT 135 should have equal frequencies or periods. In practice, this is not feasible. FIGS. 2b and 2d show two timing signals that have slightly different frequencies. The timing signal 205 has a lower frequency or a longer period than the timing signal 215. This forces the frame length of plot 205 of FIG. 2b to be longer than that of plot 215 of FIG. 2d. Further, values of the magnitudes of the digitized samples will be in error as shown in plots 200 and 205 respectively of FIGS. 2a and 2b. 
FIG. 3a illustrates the instance where timing signal of the CLKIN 115 has a longer period or lower frequency than that of the timing signal CLKOUT 135. The amplitude YIN 310 is the value of the input sample D2 300. If the frequency of the input timing signal CLKIN 115 were the same as the output timing signal CLKOUT 135, the amplitude YOUT 305 is the value that the sample D2 315 should have to produce the analog output signal 150 of FIG. 1.
Alternatively, FIG. 3b illustrates the instance where input timing signal of the CLKIN 115 has a shorter period or higher frequency than the output timing signal CLKOUT 135. As in the case of FIG. 3a, the amplitude YIN310 is the value of the input sample D2 300. As described in FIG. 3a, if the frequency of the output timing signal CLKIN 115 were the same as the output timing signal CLKOUT 135, the amplitude YOUT 305 is the value that the sample D2 315 should have to reproduce the analog signal 150 of FIG. 1.
Referring back to FIGS. 2a to 2d, if the input timing signal CLKIN 115 of FIG. 1 has a lower frequency as shown in plot 205 of FIG. 2b than the output timing signal CLKOUT 135 of FIG. 1 as shown in plot 215 of FIG. 2d, the receiver 130 will sample the output digital data that is shown in plot 200 of FIG. 2a. Since there are fewer samples of the output digital data 130 than expected during the period of one frame of the output timing signal 215, there will be an overrun of the digital data. The output timing signal 215 will receive multiple copies of samples for the output digital data 140 causing extreme distortion in the analog output signal 150.
Conversely, if the input timing signal CLKIN 115 has a higher frequency as shown in plot 215 of FIG. 2d than the output timing signal CLKOUT 135 as shown in plot 205 of FIG. 2b, the receiver 130 will sample the output digital data that is shown in plot 210 of FIG. 2c. Since there are now more samples of the output digital data 130 than expected during the period of one frame of the output timing signal 205, there will be an underrun of the digital data. The output timing signal 205 will miss capturing some of the samples of the output digital data 140. This again caused extreme distortion in the analog output signal 150.
Typically, the output timing signal 135 is synchronized to the transitions of the output digital data 110 employing a phase locked oscillator similar to those described in U.S. Pat. No. 5,577,080 (Sakaue et al.), U.S. Pat. No. 5,790,615 (Beale et al.), U.S. Pat. No. 5,652,532 (Yamaguchi), and U.S. Pat. No. 4,855,683 (Troudet et al.).
Sakaue et al. describes a digital phase-locked loop (DPLL) circuit, which achieves a high-precise phase matching between input and output clocks at high speed, irrespective of phase difference between both. The DPLL has a phase comparator for sequentially comparing an input clock with an output clock in phase and outputting phase comparison result signals. The DPLL has a random walk filter for sequentially adding and accumulating the comparison result signals inputted by the phase comparator, discriminating a relative magnitude between the obtained addition data and threshold value information, and outputting a frequency change signal corresponding to the discriminated result and the phase shift amount information. The DPLL further has a variable frequency oscillator for generating the output clock according to the frequency change signal, and a filter coefficient generating circuit for changing and outputting at least one of the outputted threshold value information and the phase shift amount information according to the phase synchronous status supplied from an operation status detecting circuit.
Beale et al. teaches a digital phase-lock loop network that provides input and output clock signals to a to a data buffer contained in digital data receiving system. The digital phase-lock loop network provides bit clock synchronization using a fixed input clock and an output clock having a variable frequency that is adjusted to correspond to the average input rate of the data samples into the data buffer. The digital phase-lock loop network allows the data buffer to be operated as a temporary storage device maintaining a nominal number of data samples therein at all times by avoiding any overflow and underflow data handling conditions that may otherwise cause loss of data. The digital phase-lock loop network of Beale et al. is particularly suited for the Eureka-147 system, which has become a worldwide standard for digital audio broadcasting (DAB) technology.
Yamaguchi sets forth a frequency difference detection circuit capable of increasing the detection sensitivity for a frequency difference and shortening the frequency difference detection time. The frequency difference detection circuit comprises a first phase locked loop (PLL) for detecting a phase difference between an input clock and an output clock in response to the input clock and performing control to gradually suppress the detected phase difference to zero, a second PLL for detecting a phase difference between the input clock and an output clock in response to the input clock and performing control to suppress the detected phase difference to zero at a speed higher than that of the first PLL. The frequency difference detection circuit further has a first phase difference detection means for detecting a phase difference between the input clock and the output clock from the first PLL and a second phase difference detection means for detecting a phase difference between the input clock and the output clock from the second PLL. A phase difference processing means processes a detection of a difference between the phase difference detected by the first and second phase difference detection means. Finally, a frequency difference detection means detects a frequency difference between the input clock and a reference frequency from a detection output from the phase difference processing means.
Troudet et al. discloses a digital phase locked loop operable over a wide dynamic range has jitter performance that is exactly bounded within predetermined limits. The phase locked loop includes an accumulator-type digital voltage controlled oscillator which generates from a high speed system clock, an output clock signal at frequency equal to p times the frequency of an input clock signal, and which output frequency is controlled by the value k of a digital input to the VCO. A frequency window comparator compares the number of output clock pulses between input clock pulses to determine, based on the count, whether the frequency of the output is too high, too low or equal to the correct frequency. A phase window comparator simultaneously determines from the phase of the output clock signal whether the phase is leading, lagging or within a prescribed window of acceptability. In response to these determinations, the k-controller increases k to increase the frequency of the VCO when the frequency window comparator indicates the frequency is low or the phase window comparator indicates the phase is lagging; alternatively, k is decreased when the frequency is high or the phase is leading. Adjustment continues until the output clock is at the proper frequency and phase of the output falls within the window of acceptability.
An object of the present invention is to provide a method and device to synchronize a frame of sampled digital data transferred from an input section to an output section. The sampled digital data indicates the magnitude of an analog electrical signal.
Another object of this invention is to prevent data overrun or underrun due to timing differences of timing signals of the input and output section.
Further, another object of this invention is to eliminate accumulation of timing misalignment of an input sampled data and an output timing signal in a digital communications system transferring digital signals representing sampled analog signals.
To accomplish these and other objects a timing synchronization device has an input sampled data counter to determine a number of samples in a frame time of the input sampled data. The timing synchronization device further has an interpolator to estimate data sample values for each sample of the input sampled data to coincide with each sample of the output sampled data if the number of samples in the input sampled data is less than an expected number of samples in the output sampled data. If the number of samples in the input sampled data is greater than the expected number of samples in the output sampled data, the timing synchronization device has a decimator to remove any excess samples of the input sampled data and to extrapolate each data sample of the input sampled data to coincide with each sample of the output sampled data. The timing synchronization device has a low pass filter connected to the interpolator and the decimator to prevent any aliasing of the output sampled data.
A calculate and control means is connected to the input sampled data counter, the interpolator, the decimator, and the low pass filter. The calculate and control means receives the number of samples in the input sampled data and compares the number of samples in the input sampled data with an expected number of samples in the output sampled data. If the number of samples in the input sampled data is less than the expected number of samples in the output sampled data, the calculate and control means causes the interpolator to estimate the data sample values. However, if the number of samples in the input sampled data is greater than the expected data, the calculate and control means causes the decimator to remove the excess samples and extrapolate each data sample. The calculate and control means determines a cutoff frequency of the low pass filter to prevent the high frequency aliasing terms.
The interpolator estimates the data sample values for each sample of the input sampled data by solving the formula:       D    2    xe2x80x2    =            D      1        +                  (                              D            2                    -                      D            1                          )            ⁢              xe2x80x83            ⁢              CNT                  CNT          expected                    
where:
D2xe2x80x2 is an estimated data sample,
D1 is a previous input data sample,
D2 is a present input data sample,
CNT is the number of samples in the input sampled data, and
CNTexpected is the number of samples expected in the output sampled data.
The decimator estimates the data sample values for each sample of the input sampled data by solving the formula:       D    2    xe2x80x2    =            D      2        +                  (                              D            2                    -                      D            1                          )            ⁢              xe2x80x83            ⁢                        CNT          -                      CNT            expected                                    CNT          expected                    
where
D2xe2x80x2 is an estimated data sample,
D1 is a previous input data sample,
D2 is a present input data sample,
CNT is the number of samples in the input sampled data, and
CNTexpected is the number of samples expected in the output sampled data.
The low pass filter convolves the input sampled data into a frequency spectrum of the input sampled data and the low pass filter performs a function of the form       sin    ⁢          xe2x80x83        ⁢    x    x
of the frequency spectrum to provide the low pass filtering.
A second embodiment of the timing synchronization device is to synchronize a timing of an input sampled data to a first timing signal to prevent data overrun and data underrun of the input sampled data due to timing differences of a second timing signal to which the input sampled data is synchronized and the first timing signal. The timing synchronization device has an input sampled data counter to determine a number of samples in the input sampled data. A count comparator compares the number of samples in the current data frame of the input sampled data with an expected number of data samples of the current data frame of the input sampled data.
If the number of input sampled data is less than the number of expected sampled data, an interpolator creates a value that is one half a sum of a magnitude of a last data sample of the input sampled data of the current data frame and a magnitude of the a first input data sample of a next data frame. The interpolator then appends the interpolated value after the last data sample of the input sampled data of the current data frame to form a current data frame of the output sampled data. However, if the number of samples in the current data frame of the input sampled data is greater than the expected number of data samples of the current data frame of the input sampled data, a decimator determines an average value of the last data sample of the current data frame and a second to last data sample of the current data frame and then inserts the average value to the second to last data sample of the current data frame. The decimator then discards the last data sample to form a current data frame of the output sampled data. The timing synchronization device may optionally have a low pass filter to filter the current frame of the output sampled data to prevent any aliasing of the output sampled data.
The synchronization of the timing of the input sampled data to prevent data overrun and data underrun of the input sampled data due to timing differences of an input sampling clock and an output sampling clock is accomplished within a signal processing system by first counting the number of input sampled data within a data frame. The number of input sampled data is compared with an expected number of input sampled data.
If the number of input sampled data is less than the number of expected sampled data, each sample of the input sampled data is interpolated to coincide with each sample of the output sampled data. Any missing sample of the output sampled data not coinciding with the input sampled data are formed by inserting new estimated data samples to the output sampled data. If the number of input sampled data is greater than the number of expected sampled data, each sample of the input sampled data is extrapolated to coincide with each sample of the output sampled data. Excess data samples not coinciding with the output sampled data are discarded. The output sampled data are then, optionally, low pass filtered to prevent any aliasing of the output sampled data.
A second embodiment of the method to synchronize a timing of an input sampled data to an output timing signal describes a method to prevent data overrun and data underrun of the input sampled data due to timing differences of an input timing signal to which the input sampled data is synchronized and the output timing signal. The method begins by counting the number of input sampled data within a current data frame. The number of input sampled data is compared with an expected number of input sampled data within the current data frame. If the number of input sampled data is more than one less than the number of expected sampled data, a magnitude that is a last data sample of the input sampled data of the current data frame and a magnitude of a first data sample of the input sampled data of a next data frame are interpolated as the average of the two magnitudes of the last data sample and the first data sample of the next data frame. The new interpolated value is then appended to the input sampled data to form a current data frame of the output sampled data. However, if the number of input sampled data of the current data frame is more than one greater than the number of expected sampled data, an average value of the last data sample of the input sampled data and a second to last data sample of the current data frame is determined. The average value is then inserted to the second to last data sample and the last data sample is discarded or decimated to form the current data frame of the output sampled data. The output sampled date may optionally be low pass filtered to prevent any aliasing of the output sampled data.